Asynchronous FIFO, enable controller, output unit register, simulation verification
Abstract
When the data processing speed is mismatched or multitasking occurs, frequent data reads may lead to a decrease in the processing efficiency of FIFO. To solve this problem, an asynchronous FIFO circuit with a prefetching function was designed based on the traditional asynchronous FIFO circuit. This circuit adds an enable controller and output unit register on the basis of the original asynchronous FIFO module. The enable controller completes the conversion between the read pointer and null pointer of the ordinary FIFO and the pre-fetch FIFO, and the output register outputs the data as read data to achieve data pre-fetch. Using Modelsim for functional verification, simulations were conducted in various modes such as writing only one data read and continuous reading after completion. The simulation results showed that the design can quickly and accurately read data from the FIFO. The design of this module can effectively improve system performance and resource utilization and has a guiding role in the future development of fields such as network communication and image and video processing.
