Microelectronics and integrated circuit technologies are undergoing continuous evolution, resulting in increasingly powerful processor chips. Presently, the predominant processors available in the market are based on the X86 and ARM architectures, both of which are proprietary and associated with substantial patent licensing constraints. In contrast, RISC-V is an entirely open-source instruction set architecture that is accessible to anyone. Given the diverse, personalized, and differentiated demands within the chip industry, the exploration and utilization of the RISC-V instruction set for processor design hold significant importance.This study first examines the RISC-V instruction set architecture, focusing on its instructional characteristics and format. Subsequently, a three-stage pipeline design is implemented based on the tinyriscv framework, incorporating resource optimizations. The study also addresses the pipeline conflict issues and proposes a partial solution. Finally, the pipeline design’s efficacy and the processor core’s fundamental instructions are validated through ModelSim simulations and the development of test programs.
